That seems to be a cable for Elite : I did the same....
A ver si te ha dicho que de qué "wataje" (que viene de "watt", watio-potencia) las queríasesta mañana he ido a comprar todos los componentes y a la hora de comr las 8 resisitencias de 120 ohmios me dice el voltaje con que las quiero, ya que hay de varios voltajes , me gustaria que me dijerais cual tiene que ser y por lo que estoy leyendo ese puede ser uno de los problemas, muchas gracias y salu2
pins
db-elite jtag
2-11
3-9
4-7
5-5
13-3
20-2
it's not same !?!
With this cabling, the cable does'nt work : It's like no cable was connected
But I'm practically sure the solution is there : On all others receivers, the Jtag requires 6 wires connected to parallel port
Probably the initial document was wrong, but this one too
Who can give us the good wiring ?
Below is the Parallel port DB25 pinout :
Pinouts
Pinouts for parallel port connectors are:
Pin No (DB25) Pin No (36 pin) Signal name Direction Register - bit Inverted
1 1 Strobe In/Out Control-0 Yes
2 2 Data0 Out Data-0 No
3 3 Data1 Out Data-1 No
4 4 Data2 Out Data-2 No
5 5 Data3 Out Data-3 No
6 6 Data4 Out Data-4 No
7 7 Data5 Out Data-5 No
8 8 Data6 Out Data-6 No
9 9 Data7 Out Data-7 No
10 10 Ack In Status-6 No
11 11 Busy In Status-7 Yes
12 12 Paper-Out In Status-5 No
13 13 Select In Status-4 No
14 14 Linefeed In/Out Control-1 Yes
15 32 Error In Status-3 No
16 31 Reset In/Out Control-2 No
17 36 Select-Printer In/Out Control-3 Yes
18-25 19-30,33,17,16 Ground - - -
TCK: [Test Clock] has noting to do with the board or system clock. The Test Clock is used to load the test mode data from the TMS pin, and the test data on the TDI pin [on the rising edge]. On the falling edge test clock outputs the test data on the TDO pin. As with any clock pin this line needs to be terminated in order to reduce reflections. The termination should be a 68 ohm resistor in series with a 100pF capacitor to ground. The TCK signal is bused to all Integrated Circuits [IC] in the JTAG chain. The signal may require buffering or be fanned out by multiple drivers depending on the distance and number of devices in the chain. Using multiple drivers would also require a termination resistor on each TCK line.
TMS: [Test Mode Select Input] controls the operation of the test logic, by receiving the incoming data]. The value at the input on the rising edge of the clock controls the movement through the states of the TAP controller. The TMS line has an internal pull-up, so the input is high with no input. The TMS signal is bused to all ICs in the JTAG chain. The TMS line should have a 10k pull-up resistor on the line.
TDI: [Test Data Input] receives serial input data which is either feed to the test data registers or instruction register, but depends on the state of the TAP controller. The TDI line has an internal pull-up, so the input is high with no input. The TDI signal is feed to the TDI pin of the first IC in the JTAG chain. The TDO signal from that IC is then sent to the TDI pin of the next IC in the chain or sent back out to the JTAG header. The TDI line should have a 10k pull-up resistor on the line.
TDO: [Test Data Output] outputs serial data which comes from either the test data registers or instruction register, but depends on the state of the TAP controller. Data applies to the TDI pin will appear at the TDO pin but may be shifted of a number of clock cycles, depending on the length of the internal register. The TDO pin is high-Impedance. The TDO signal is the output from a JTAG device that feed the TDI input of another JTAG device. The TDO line should have a 10k pull-up resistor on the line. The TDO signal should also include a 22 ohm series resistor placed near the last device in the JTAG chain.
TRST: [Test Rest] will asynchronously reset the JTAG test logic. The logic is reset (with TRST) regardless of the state of TMS or TCLK. The TRST signal is bused to all ICs in the JTAG chain. The TRST signal should include a pull-down resistor when possible to reduce the chance the signal floats.